/*
 * tas2552.h  --  smart PA driver for TAS2552
 *
 * Copyright (C) 2017 XiaoMi, Inc.
 *
 * Author: Nannan Wang <wangnannan@xiaomi.com>
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 *
*/


#ifndef TAS2552_H_
#define TAS2552_H_

#define TAS2552_REG_DEVICE_STATUS				0x00
#define TAS2552_REG_CONFIG1					0x01
#define TAS2552_REG_CONFIG2					0x02
#define TAS2552_REG_CONFIG3					0x03
#define TAS2552_REG_DOUT_TRISTATE_MODE				0x04
#define TAS2552_REG_I2SCTRL1					0x05
#define TAS2552_REG_I2SCTRL2					0x06
#define TAS2552_REG_OUTPUT_DATA					0x07
#define TAS2552_REG_PLLCTRL1					0x08
#define TAS2552_REG_PLLCTRL2					0x09
#define TAS2552_REG_PLLCTRL3					0x0A
#define TAS2552_REG_BATTERY_GUARD_INFLECTION_PT			0x0B
#define TAS2552_REG_BATTERY_GUARD_SLOPE_CTRL			0x0C
#define TAS2552_REG_LIMITER_LEVEL_CTRL				0x0D
#define TAS2552_REG_LIMITER_AR_HT				0x0E
#define TAS2552_REG_LIMITER_RELEASE_RATE			0x0F
#define TAS2552_REG_LIMITER_INTEGRATION_COUNT_CTRL		0x10
#define TAS2552_REG_PDM_CONFIG					0x11
#define TAS2552_REG_PGA_GAIN					0x12
#define TAS2552_REG_CLASS_D_EDGE_RATE_CTRL			0x13
#define TAS2552_REG_BOOST_AUTO_PASS_THROUGH_CTRL		0x14
#define TAS2552_REG_RESERVED					0x15
#define TAS2552_REG_VERSION_NUMBER				0x16	/* Read Only */
#define TAS2552_REG_INTERRUPT_MASK				0x17
#define TAS2552_REG_VBOOST_DATA					0x18	/* Read Only */
#define TAS2552_REG_VBAT_DATA					0x19	/* Read Only */


/* Register bits */
/* TAS2552_REG_CONFIG1 (0x01) */
#define TAS2552_CONFIG1_SWS_MSK				0x2
#define TAS2552_CONFIG1_SWS				(0x1 << 1)

#define TAS2552_CONFIG1_MUTE_MSK			0x4
#define TAS2552_CONFIG1_MUTE				(0x1 << 2)

#define TAS2552_CONFIG1_PLL_SRC_MSK			0x30
#define TAS2552_CONFIG1_PLL_SRC_POS			4
#define TAS2552_CONFIG1_PLL_SRC_MCLK			0x0
#define TAS2552_CONFIG1_PLL_SRC_BCLK			(0x1 << TAS2552_CONFIG1_PLL_SRC_POS)
#define TAS2552_CONFIG1_PLL_SRC_IVCLKIN			(0x2 << TAS2552_CONFIG1_PLL_SRC_POS)
#define TAS2552_CONFIG1_PLL_SRC_INTERNAL_1P8		(0x3 << TAS2552_CONFIG1_PLL_SRC_POS)

/* TAS2552_REG_CONFIG2 (0x02) */
#define TAS2552_CONFIG2_INIT_MSK			0x1
#define TAS2552_CONFIG2_INIT_DEFAULT			0x1
#define TAS2552_CONFIG2_INIT_EN				0x0

#define TAS2552_CONFIG2_PLL_EN_MSK			0x8
#define TAS2552_CONFIG2_PLL_EN_POS			3
#define TAS2552_CONFIG2_PLL_EN_ENABLE			(0x1 << TAS2552_CONFIG2_PLL_EN_POS)

/* TAS2552_REG_CONFIG3 (0x03) */
#define TAS2552_CONFIG3_WCLK_MSK			0x7
#define TAS2552_CONFIG3_WCLK_POS			0
#define TAS2552_CONFIG3_WCLK_8000			0x0
#define TAS2552_CONFIG3_WCLK_11025_12000		0x1
#define TAS2552_CONFIG3_WCLK_16000			0x2
#define TAS2552_CONFIG3_WCLK_22050_24000		0x3
#define TAS2552_CONFIG3_WCLK_32000			0x4
#define TAS2552_CONFIG3_WCLK_44100_48000		0x5
#define TAS2552_CONFIG3_WCLK_88200_96000		0x6
#define TAS2552_CONFIG3_WCLK_176400_192000		0x7

#define TAS2552_CONFIG3_SOURCE_SELECT_MSK		0x18
#define TAS2552_CONFIG3_SOURCE_SELECT_POS		3
#define TAS2552_CONFIG3_SOURCE_SELECT_MAX		3
#define TAS2552_CONFIG3_SOURCE_SELECT_NONE		0x0
#define TAS2552_CONFIG3_SOURCE_SELECT_LEFT		(0x1 << TAS2552_CONFIG3_SOURCE_SELECT_POS)
#define TAS2552_CONFIG3_SOURCE_SELECT_RIGHT		(0x2 << TAS2552_CONFIG3_SOURCE_SELECT_POS)
#define TAS2552_CONFIG3_SOURCE_SELECT_MONO		(0x3 << TAS2552_CONFIG3_SOURCE_SELECT_POS)

/* TAS2552_REG_I2SCTRL1 (0x05) */
#define TAS2552_I2SCTRL1_PCM_FMT_MSK			0x3
#define TAS2552_I2SCTRL1_PCM_FMT_POS			0
#define TAS2552_I2SCTRL1_PCM_FMT_16			0x0
#define TAS2552_I2SCTRL1_PCM_FMT_20			0x1
#define TAS2552_I2SCTRL1_PCM_FMT_24			0x2
#define TAS2552_I2SCTRL1_PCM_FMT_32			0x3

#define TAS2552_I2SCTRL1_PCM_DATAFMT_MSK		0xC
#define TAS2552_I2SCTRL1_PCM_DATAFMT_POS		2
#define TAS2552_I2SCTRL1_PCM_DATAFMT_I2S		0x0
#define TAS2552_I2SCTRL1_PCM_DATAFMT_DSP		(0x1 << TAS2552_I2SCTRL1_PCM_DATAFMT_POS)
#define TAS2552_I2SCTRL1_PCM_DATAFMT_RJF		(0x2 << TAS2552_I2SCTRL1_PCM_DATAFMT_POS)
#define TAS2552_I2SCTRL1_PCM_DATAFMT_LJF		(0x3 << TAS2552_I2SCTRL1_PCM_DATAFMT_POS)

#define TAS2552_I2SCTRL1_PCM_BCLK_MSK			0x30
#define TAS2552_I2SCTRL1_PCM_BCLK_POS			4
#define TAS2552_I2SCTRL1_PCM_BCLK_32			0x0
#define TAS2552_I2SCTRL1_PCM_BCLK_64			(0x1 << TAS2552_I2SCTRL1_PCM_BCLK_POS)
#define TAS2552_I2SCTRL1_PCM_BCLK_128			(0x2 << TAS2552_I2SCTRL1_PCM_BCLK_POS)
#define TAS2552_I2SCTRL1_PCM_BCLK_256			(0x3 << TAS2552_I2SCTRL1_PCM_BCLK_POS)

#define TAS2552_I2SCTRL1_PCM_BCLKDIR_MSK		0x40
#define TAS2552_I2SCTRL1_PCM_BCLKDIR_POS		6
#define TAS2552_I2SCTRL1_PCM_BCLKDIR_OUTPUT		(0x1 << TAS2552_I2SCTRL1_PCM_BCLKDIR_POS)

#define TAS2552_I2SCTRL1_PCM_WCLKDIR_MSK		0x80
#define TAS2552_I2SCTRL1_PCM_WCLKDIR_POS		7
#define TAS2552_I2SCTRL1_PCM_WCLKDIR_OUTPUT		(0x1 << TAS2552_I2SCTRL1_PCM_WCLKDIR_POS)

/* TAS2552_REG_PLLCTRL1 (0x08) */
#define TAS2552_PLLCTRL1_J_MSK				0x7F

#define TAS2552_PLLCTRL1_P_MSK				0x80
#define TAS2552_PLLCTRL1_P_POS				7

/* TAS2552_REG_PLLCTRL2 (0x09) */
#define TAS2552_PLLCTRL2_D_BIT13_8_MSK			0x3F

#define TAS2552_PLLCTRL2_BYPASS_MSK			0x80
#define TAS2552_PLLCTRL2_BYPASS_POS			7

/* TAS2552_REG_PLLCTRL3 (0x0A) */
#define TAS2552_PLLCTRL3_D_BIT7_0_MSK			0xFF

/* TAS2552_REG_LIMITER_LEVEL_CTRL (0x0D) */
#define TAS2552_LIMITER_LEVEL_CTRL_INIT_MSK		0xFF
#define TAS2552_LIMITER_LEVEL_CTRL_INIT_DEFAULT		0xBE
#define TAS2552_LIMITER_LEVEL_CTRL_INIT_EN		0xC0

/* TAS2552_REG_LIMITER_AR_HT (0x0E) */
#define TAS2552_LIMITER_AR_HT_INIT_MSK			0x20
#define TAS2552_LIMITER_AR_HT_INIT_POS			5
#define TAS2552_LIMITER_AR_HT_INIT_DEFAULT		0x0
#define TAS2552_LIMITER_AR_HT_INIT_EN			(0x1 << TAS2552_LIMITER_AR_HT_INIT_POS)

/* TAS2552_REG_PGA_GAIN (0x12) */
#define TAS2552_PGA_GAIN_POS				0
#define TAS2552_PAG_GAIN_MAX				0x1F


/* system clock source */
enum {
	TAS2552_SCLK_S_MCLK,
	TAS2552_SCLK_S_BCLK,
	TAS2552_SCLK_S_IVCLKIN,
	TAS2552_SCLK_S_INTERNAL_1P8,
};
#endif /* TAS2552_H_ */
